SKILL.md
Tailslayer — DRAM Hedged Read Library
Skill by ara.so — Daily 2026 Skills collection.
Tailslayer is a C++ library that reduces tail latency in RAM reads caused by DRAM refresh stalls. It replicates data across multiple independent DRAM channels with uncorrelated refresh schedules, issues hedged reads across all replicas simultaneously, and returns whichever result responds first — eliminating worst-case stall spikes from DRAM refresh cycles.
Works on AMD, Intel, and AWS Graviton using undocumented channel scrambling offsets.
How It Works
- Data is replicated N times, each copy placed on a different DRAM channel
- Each replica is monitored by a worker pinned to a separate CPU core
- When a read is triggered (via your signal function), all replicas are read simultaneously
- Whichever channel responds first wins; the result is passed to your work function
- DRAM refresh on one channel cannot stall all channels simultaneously → tail latency is eliminated
Tailslayer — DRAM Hedged Read Library
Skill by ara.so — Daily 2026 Skills collection.
Tailslayer is a C++ library that reduces tail latency in RAM reads caused by DRAM refresh stalls. It replicates data across multiple independent DRAM channels with uncorrelated refresh schedules, issues hedged reads across all replicas simultaneously, and returns whichever result responds first — eliminating worst-case stall spikes from DRAM refresh cycles.
Works on AMD, Intel, and AWS Graviton using undocumented channel scrambling offsets.
How It Works
- Data is replicated N times, each copy placed on a different DRAM channel
- Each replica is monitored by a worker pinned to a separate CPU core
- When a read is triggered (via your signal function), all replicas are read simultaneously
- Whichever channel responds first wins; the result is passed to your work function
- DRAM refresh on one channel cannot stall all channels simultaneously → tail latency is eliminated